www.siliconstandard.com 1 of 6 SSM6618M n-channel enhancement-mode power mosfet low on-resistance bv dss 25v fast switching speed r ds(on) 30mw surface-mount package i d 7a description absolute maximum ratings symbol units v ds v v gs v i d @ t a =25c i d @ t a =70c i dm a p d @ t a =25c w/c t stg t j symbol value unit rthj-amb thermal resistance junction-ambient max. 50 cw parameter rating drain-source voltage 25 gate-source voltage 20 continuous drain current 3 7 a continuous drain current 3 5.8 a pulsed drain current 1,2 30 total power dissipation 2.5 w -55 to 150 c operating junction temperature range -55 to 150 c linear derating factor 0.02 thermal data parameter storage temperature range power mosfets from silicon standard provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. s s s g d d d d so-8 g d s re v . 2.02 3/21/2004
www.siliconstandard.com 2 of 6 SSM6618M electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 25 - - v d bv dss /d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.02 - v/c r ds(on) static drain-source on-resistance v gs =10v, i d =7a - - 30 mw v gs =4.5v, i d =5a - - 50 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =7a - 13 - s i dss drain-source leakage current (t j =25 o c) v ds =25v, v gs =0v - - 1 ua drain-source leakage current (t j =70 o c) v ds =20v ,v gs =0v - - 25 ua i gss gate-source leakage v gs = 20v - - 100 na q g total gate charge 2 i d =7a - 8.4 - nc q gs gate-source charge v ds =20v - 2.1 - nc q gd gate-drain ("miller") charge v gs =4.5v - 4.7 - nc t d(on) turn-on delay time 2 v ds =15v - 6 - ns t r rise time i d =1a - 5.2 - ns t d(off) turn-off delay time r g =3.3w ,v gs =10v - 18.8 - ns t f fall time r d =15 w - 4.4 - ns c iss input capacitance v gs =0v - 645 - pf c oss output capacitance v ds =25v - 150 - pf c rss reverse transfer capacitance f=1.0mhz - 95 - pf source-drain diode symbol parameter test conditions min. typ. max. units i s continuous source current ( body diode ) v d =v g =0v , v s =1.2v - - 7 a i sm pulsed source current ( body diode ) 1 --3 0 a v sd forward on voltage 2 t j =25c, i s =7a, v gs =0v - - 1.2 v notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on fr4 board, t< 10 sec. re v . 2.02 3/21/2004
www.siliconstandard.com 3 of 6 SSM6618M fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature 0 12 24 36 02356 v ds , drain-to-source voltage (v) i d , drain c urrent (a) t c =150 o c 10v 8.0v 6.0v 5.0v v gs =4.5v 0 12 24 36 02356 v ds , drain-to-source voltage (v) i d , drain c urrent (a) t c =25 o c 10v 8.0v 6.0v 5.0v v gs =4.5v 0.2 0.8 1.4 2 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =7.0a v gs =10v 0 20 40 60 80 2 6 10 14 v gs (v) r ds(on) (m ) i d =7.0a t c =25 re v . 2.02 3/21/2004
www.siliconstandard.com 4 of 6 SSM6618M fig 5. maximum drain current vs. fig 6. typical power dissipation case temperature fig 7. maximum safe operating area fig 8. effective transient thermal impedance 0.1 1 10 100 0.1 1 10 100 v ds (v) i d (a) t c =25 o c s in g le pulse 1ms 10ms 100ms 1s 10s 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a t t 0.02 0.01 0.05 0.1 0.2 duty factor = 0.5 single pulse 0 2 4 6 8 25 50 75 100 125 150 t c , case temperature ( o c) i d , drain c urrent (a) 0 1 2 3 0 50 100 150 t c , case temperature ( o c) p d (w) re v . 2.02 3/21/2004
www.siliconstandard.com 5 of 6 SSM6618M fig 9. gate charge characteristics fig 10. typical capacitance characteristics fig 11. forward characteristic of fig 12. gate threshold voltage vs. reverse diode junction temperature 0 0.5 1 1.5 2 2.5 3 -50 0 50 100 150 t j , junction temperature ( o c ) v gs(th) (v) 0 3 6 9 12 048121 6 q g , total gate charge (nc) v gs , gate to source voltage (v) i d =7a v ds =12v v ds =16v v ds =20v 10 100 1000 10000 1 7 13 19 25 31 v ds (v) c (pf) f =1.0mhz ciss coss crss 0.01 0.1 1 10 100 0 0.4 0.8 1.2 v sd (v) i s (a) tj=25 o ctj=150 o c re v . 2.02 3/21/2004
www.siliconstandard.com 6 of 6 in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. SSM6618M fig 13. switching time circuit fig 14. switching time waveform fig 15. gate charge circuit fig 16. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge 0.8 x rated v ds to the oscilloscope - + d g s v ds v gs i d i g 1~ 3 m a 0.6 x rated v ds to the oscilloscope - + 10 v d g s v ds v gs r g r d re v . 2.02 3/21/2004
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